The present invention relates to a method of manufacturing a semiconductor device with accurately dimensioned interconnection patterns and exhibiting reduced capacitance loading. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
As integrated circuit geometries continue to plunge deeper into the submicron regime, it becomes increasingly difficult to satisfy the demands for dimensional accuracy. Moreover, interconnection technology is constantly challenged to satisfy the ever increasing requirements for high performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a patterned conductive level comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. The excess conductive material or overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a lower contact or via in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-a-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSIN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD), bat includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, is formed over an underlying pattern having a capping layer thereon, e.g., a Cu or Cu alloy pattern with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of a dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have bee explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9. One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). Such polymers and their use are disclosed in, for example, U.S. Pat. Nos. 4,756,977 and 5,981,354. HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to vulnerable to degradation during various fabrication steps, including plasma etching. Methods involving plasma treatment have been developed to address such problems attendant upon employing HSQ-type flowable oxides as a gap filling layer, as in the U.S. Pat. No. 5,866,945 and U.S. Pat. No. 6,083,851.
There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which offer promise for use as an ILD. As used throughout this disclosure, the term xe2x80x9corganicxe2x80x9d is intended to exclude HSQ type materials, e.g., flowable oxides and ceramic polymers, which are not true organic materials. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 2.0(trademark) dielectric, a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif., Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif., BCB (divinylsiloxane bis-benzocyclobutene) and Silks(trademark) an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich.
In implementing conventional damascene techniques, such as dual damascene techniques, the organic photoresist mask is typically removed employing an oxygen (O2) plasma stripping technique after forming an opening in a dielectric layer, such as a via hole, trench or dual damascene technique comprising a lower via hole in communication with an upper trench however, in attempting to employ organic low-k materials in such interconnect technology, e.g., as an ILD, the O2 plasma stripping technique disadvantageously also strips off and degrades a portion the organic low-k material, thereby adversely impacting device geometry and performance.
There exists a need for methodology enabling the use organic of low-k dielectric materials as an ILD in high density, multilevel interconnection patterns. There exist a particular need for methodology enabling the use of such organic low-k materials in damascene technology without removal or damage during photoresist stripping.
An advantage of the present invention is a method of manufacturing a semiconductor device with accurately dimensioned interconnection patterns, particularly Cu and/or Cu alloy interconnection patterns, and exhibiting reduced parasitic RC time delays employing organic dielectric materials having a low dielectric constant.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer on a first capping layer overlying a lower metal level; forming a silicon carbide hard mask on the first dielectric layer; and etching to form a first opening having a cross-sectional width through the first dielectric layer exposing a portion of the capping layer.
Embodiments of the present invention comprise forming a via opening in the first dielectric layer, forming a second dielectric layer on the silicon carbide hard mask, forming a second capping layer on the second dielectric layer, forming a photoresist mask over the second capping layer, and anisotopically etching to form a trench opening, having a width greater than the cross-sectional width of the via opening, through the second capping layer and second dielectric layer while the silicon carbide hard mask advantageously protects the upper surface of the first dielectric layer under the trench. Etching is continued to remove exposed portions of the silicon carbide mask in the damascene opening, and through the exposed portion of the first capping layer exposing a portion of the lower metal feature. Embodiments of the present invention include filling the openings with Cu or a Cu alloy layer followed by planarization, as by chemical mechanical polishing (CMP), with subsequent deposition of a capping layer, such as silicon nitride.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded and illustrative in nature, and not as restrictive